In a move that could reshape the trajectory of global computing, Huawei has unveiled a groundbreaking architectural framework designed to unlock a massive leap in semiconductor performance and power efficiency.
Delivering a keynote address titled “New Semiconductor Path in Practice” at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Huawei’s He Tingbo introduced the “Tau Scaling Law.” This new principle positions itself as a successor to traditional manufacturing paradigms, proposing a shift from physical geometric scaling—shrinking the physical size of transistors—to time scaling as the primary vehicle for driving next-generation electronic systems forward.
For decades, the semiconductor industry has chased raw power by squeezing more transistors onto smaller silicon dies. However, as physics boundaries tighten and cost-per-transistor benefits erode, the industry has neared a critical bottleneck. Huawei’s Tau Scaling Law circumvents these physical limitations by focusing systematically on shortening the time constant $\tau$, compressing signal propagation delays to achieve massive efficiency gains rather than relying solely on traditional fabrication shrinks.
To realize this leap in power, Huawei has established a multi-level co-optimization mechanism that spans the entire hardware stack, beginning at the foundational device layer. Here, engineers are optimizing the resistance and parasitic capacitance of transistors and interconnects to minimize delays at the underlying physical layer. At the circuit level, the framework introduces “LogicFolding” architecture, which shatters traditional physical layout boundaries to shorten critical-path wiring, slashing the resistive and capacitive loads that slow down signal propagation and boosting layout density.
Moving higher up the stack, the chip-level design employs a full-stack coordinated strategy combining software, architecture, and silicon. This approach grants fine-grained, workload-driven control over instruction and data flows, which maximizes system-level parallelism and efficiency while cutting down end-to-end execution time. Finally, at the system level, Huawei is redefining interconnect protocols for massive computing systems with UnifiedBus, enabling unified memory addressing and native memory semantics for SuperPoDs to virtually eliminate communication latency.
The technology is already moving rapidly from theoretical physics into commercial reality. Huawei revealed that it has spent the last six years designing and mass-producing 381 chips based on the Tau Scaling Law to seed various industry sectors. The upcoming Kirin smartphone chips, scheduled to debut in Fall 2026, will mark the first commercial deployment of the performance-boosting LogicFolding architecture. By 2031, Huawei projects that this temporal scaling methodology will allow its high-end chips to achieve an astronomical transistor density equivalent to a 14 A˚ (1.4 nm) process, securing a competitive, sustainable evolution path for high-performance AI and consumer computing.
Recognizing the global scale of the silicon challenge, Huawei concluded the announcement with a call for international teamwork. He Tingbo emphasized that openness and collaboration remain key to driving ongoing progress, noting that no single company can independently find all the answers along the path of semiconductor evolution. With the launch of the Tau Scaling Law, Huawei aims to work closely with scientists, engineers, and industry partners around the world to drive the sustainable development of the broader electronics industry.
